64-bit RISC-V Execution Unit
Digital Systems Design - ENSC 350, SFU (Apr - May 2026)
In this project, I designed and verified a modular 64-bit RISC-V execution unit in VHDL that
implemented arithmetic, logical, comparison, branch, and configurable barrel shifter operations for
FPGA implementation. I developed and compared several adder architectures, including Ripple Carry,
Carry-Select, and Kogge-Stone designs, to evaluate hardware resource utilization and timing
performance on Cyclone IV and Arria II FPGAs. I also created a comprehensive ModelSim testbench with
automated test vectors to verify functionality and synthesized each design in Intel Quartus Prime to
analyze RTL structures, FPGA resource usage, and worst-case propagation delays. The image
shows the baseline Ripple Carry Adder used as the foundation of the execution unit.